This invention relates to circuitry for testing the integrity of logic systems in general and more particularly relates to circuitry for testing logic delay timers during normal operation of an automation system in which the timer remains installed in its normal operating environment, without effectuating spurious outputs of the timer due to the testing sequence.
Logic systems normally used in automation technology frequently include timing circuits whose outputs are adapted to be activated a fixed length of time after the energizing of the timer input. Equipment which uses a delay timer for a critical activation or protection function will obviously be adversely affected if the timer fails to operate in the desired manner. A timer of this type normally requires that the master input signal exist for a time period of longer duration than the internal delay time. The timer output signal then appears at the end of the internal delay time and is present until the cessation of the master input signal. Improper operation of such a delay timer may result in either an output appearing with a delay shorter than the predetermined internal delay, including the case of no delay at all, or the output appearing with a delay longer than the predetermined internal delay, including the case of an output never appearing. The first mentioned type of timer delay failure is considered to be safe because, while causing untimely stoppage of the controlled installation, such failures do not jeopardize the safety of the installation through lack of activation or protection. The latter mentioned type of timer delay failure is considered to be unsafe because the controlled installation will not be protected in time, if at all. The first type of failure is self-revealing. The second type of failure can be revealed only through the use of special checking operations.
Procedures to test a logic system usually require that the system be temporarily removed from useful service while a test sequence which stimulates the delay timer and checks the timely appearance of the delayed output signal is completed. As the interval between such test sequences decreases, the confidence factor for isolating a delay timer failure increases but the percentage of usable equipment time decreases.